1. Field of the Invention
The present invention relates to ROM bit cell arrays and methods of generating layouts for such ROM bit cell arrays.
2. Description of the Prior Art
High density ROM bit cell arrays composed of columns of bit cells have been achieved by implementing arrangements in which adjacent bit cells in the same column share a source/drain connection to an adjacent bit line or virtual ground line.
In U.S. Pat. No. 5,917,224 a compact ROM matrix is disclosed in which two adjacent columns of bit cells share a virtual ground line. FIG. 1 schematically illustrates the arrangement disclosed. A ROM bit cell array 10 is composed of transistors 12 arranged in columns, of which only three (14, 16 and 18) are shown. A high density of cells is achieved in the vertical direction by virtue of adjacent bit cells in each column sharing source or drain (generically referred to herein as “drain”) connections. These drain connections connect each transistor in each column to either a virtual ground line shared with an adjacent column of transistors or to a bit line uniquely associated with that particular column. For example the two transistors 12a and 12b illustrated in column 18 share a common drain connection to bit line BL2. Transistor 12a shares a drain connection with the transistor above it to virtual ground line 20, whilst transistor 12b shares a drain connection with the transistor below it to bit line BL2. Each transistor encodes a logical “0” or “1” by both its drain connections connecting to the same line (bit or virtual ground) or by one drain connection connecting to each kind of line. Thus when a particular bit line is charged (e.g. BL2) and a particular word line enabled (e.g. WL1), then the transistor located at the intersection of those lines (in this example transistor 12a) will manifest the logical “0” encoded by its drain connections by discharging bit line BL2 onto virtual ground line 20. Conversely if word line WL2 were enabled instead (in order to read transistor 12b), no significant discharge of the bit line would occur (both drains of transistor 12b connect to the same line), indicating a logical “1” encoded by its drain connections (it will be understood that the encoding of “1” and “0” described above is merely a convention choice and could be trivially inverted). Columns 16 and 18 share virtual ground line 20, and have their own bit lines BL1 and BL2, respectively. Similarly column 14 shares virtual ground line 22 with the column of transistors to its left (not illustrated) and has its own dedicated bit line BL0. The transistors 12 are switched in rows by word lines WL0, WL1, WL2 and WL3. For clarity the word lines are not fully illustrated.
In U.S. Pat. No. 7,002,827 a ROM array is disclosed in which a column of bit cells shares a virtual ground line with an adjacent column of bit cells on one side and shares a bit line with an adjacent column of bit cells on the other side. FIG. 2 schematically illustrates the arrangement disclosed. A ROM bit cell array 100 is composed of transistors 110 arranged in columns, of which only three (120, 130 and 140) are shown. As in the arrangement shown in FIG. 1, a high density of cells is achieved in the vertical direction by virtue of adjacent bit cells in each column sharing drain connections. In this arrangement a greater density in the horizontal direction is achieved by virtue of the fact that the drain connections connect each transistor in each column to either a virtual ground line shared with an adjacent column of transistors on one side or to a bit line shared with an adjacent column of transistors on the other side. For example the two transistors 110a and 110b illustrated in column 140 share a common drain connection to bit line BL1. Transistor 110a shares a drain connection with the transistor above it to virtual ground line 150, whilst transistor 110b shares a drain connection with the transistor below it to bit line BL1. The logical values encoded in each transistor by virtue of its drain connections are as described above with reference to FIG. 1. Columns 130 and 140 share virtual ground line 150 situated between them, whilst sharing a bit line with an adjacent column on their respective opposite sides. Hence column 130 shares bit line BL0 with column 120 and column 140 shares bit line BL1 with a column to its right (not illustrated). Similarly column 120 shares virtual ground line 160 with the column of transistors to its left (not illustrated). As in FIG. 1, word lines WL0, WL1, WL2 and WL3 are not fully illustrated for clarity.
The densities of bit cells achieved by the two prior art arrangements described above are not however without associated cost. For example, in the arrangement of U.S. Pat. No. 5,917,224 the coupling capacitance between the adjacent bit lines (e.g. BL0 and BL1) can be problematically high, especially for bit lines which have a large number of transistors connected thereto. On the other hand the arrangement of U.S. Pat. No. 7,002,827 for example requires more complex readout logic, to ensure that the measured discharge of a given bit line is caused by the bit cell intended to be read.
These highly compact ROM bit cell arrays enable a high density of bit cells to be arranged in a given area, in particular by virtue of having geometries that operate close to the diffusion limit i.e. the spacing between the active areas of the columns of bit cells cannot be reduced any further. In this context the active area of a bit cell will be understood to correspond at the mask level to the shape which is physically used to define the drains and channel of a MOS (metal-oxide-semiconductor) device. This can be seen from FIG. 12, representing a layout view and a cross-section view of a MOS transistor. The rectangle labelled “active area” (layout view) defines the area within which the active area is created, resulting in (cross-section view) two regions of active area (due to the poly (gate) having been deposited at an earlier stage of the process).
In addition, the creation of such high density ROM devices is a complex task, involving not only the layout of the bit cell array itself, but also the associated control circuitry, word line decoders and bit line decoders required to control and read out the bit cell array. Due to this complexity it is known for the creation process to re-use an existing arrangement of control circuitry, word line decoders and bit line decoders. The particular arrangement of bit cells in the bit cell array is then generated (“compiled”) in accordance with specified requirements for that instance of ROM device. However the flexibility available to the system designer re-using control circuitry, word line decoders and bit line decoders in this manner is limited by the fact that an imposed constraint of reusing control circuitry is that the layout of word lines, bit lines and virtual ground lines is fixed (in order to correctly interface to the decoders). Furthermore, the additional constraints imposed by such high density ROM devices having geometries that operate close to the diffusion limit result in the flexibility afforded to the system designer in tuning the characteristics of the ROM bit cell array being still further limited.
It would be desirable to provide an improved technique for generating ROM bit cell arrays.